1. Technical Field
Various embodiments of the present invention relate to a semiconductor circuit and, more particularly, to a three-dimensional stacked semiconductor integrated circuit.
2. Related Art
A semiconductor integrated circuit generally includes two or more chips for purposes of improving integration efficiency. Recently, there has been developed a three-dimensional, stacked semiconductor integrated circuit having an interface of a plurality of chips by using through-silicon vias (TSVs).
FIG. 1 is a cross-sectional view of a conventional three-dimensional, stacked semiconductor integrated circuit. Referring to FIG. 1, a three-dimensional stacked semiconductor integrated circuit 1 may include a plurality of slices (e.g., a plurality of chips CHIP0 to CHIP3) stacked on a substrate 2 and connected to one another through a plurality of TSVs.
FIG. 2 is a block diagram of a conventional three-dimensional, stacked semiconductor integrated circuit. As shown in FIG. 2, a three-dimensional stacked semiconductor integrated circuit 10 may include a plurality of slices coupled to one another through a plurality of TSVs.
The plurality of slices may include a master slice MASTER_SLICE 20 and a plurality of slave slices SLAVE_SLICE0 to SLAVE_SLICE3. For simplicity, FIG. 2 illustrates only one slave slice SLAVE_SLICE3 30. Each of slave slices SLAVE_SLICE0 to SLAVE_SLICE3 may include a plurality of memory banks.
Master slice MASTER_SLICE 20 includes a decoding block 21 and a driver 22. Decoding block 21 decodes a command CMD by using a clock signal CLK to generate active control signals RACT<0:15>_S0 to RACT<0:15>_S3. Driver 22 drives active control signals RACT<0:15>_S0 to RACT<0:15>_S3 and transmits the driven active control signals RACT<0:15>_S0 to RACT<0:15>_S3 through the plurality of TSVs.
Slave slice SLAVE_SLICE3 includes a receiver 31 and a bank control unit 32. Receiver 31 receives active control signal RACT<0:15>_S3 related to receiver 31 among active control signals RACT<0:15>_S0 to RACT<0:15>_S3 transmitted through the plurality of TSVs, and transmits active control signal RACT<0:15>_S3 to bank control unit 32.
Bank control unit 32 controls the active and precharge operations of a corresponding memory bank in response to active control signal RACT<0:15>_S3.
As shown in FIG. 2, among active control signals RACT<0:15>_S0 to RACT<0:15>_S3, active control signal RACT<0>_S3 for controlling the active and precharge operations of 0th bank of a third slice SLICE3 is a level signal. That is, active control signal RACT<0>_S3 defines the active of a corresponding bank during a high level duration and defines the precharge of the corresponding bank during a low level duration.
As described above, since active control signals RACT<0:15>_S0 to RACT<0:15>_S3 are duration signals, if one of them influences other signals, a certain memory bank may be switched to operation states different from the associated command. For this reason, active control signals RACT<0:15>_S0 to RACT<0:15>_S3 are independently transmitted.
Active control signals RACT<0:15>_S0 to RACT<0:15>_S3 include four slave slices SLAVE_SLICE0 to SLAVE_SLICE3, each of which includes 16 memory banks. Thus, active control signals RACT<0:15>_S0 to RACT<0:15>_S3 are based on a total of 64 memory banks. Accordingly, in order to transmit active control signals RACT<0:15>_S0 to RACT<0:15>_S3, a total of 64 TSVs are required.
In the above-described conventional semiconductor integrated circuit, TSVs corresponding to the number of memory banks are required in order to transfer the active control signals from the master slice to the slave slices.
Although not shown in the drawings, in addition to active control signals RACT<0:15>_S0 to RACT<0:15>_S3, a plurality of TSVs such as TSVs for data transfer are provided between the master slice and the slave slices.